SDRAM (synchronous DRAM) is a generic name for various kinds of dynamic random access memory (DRAM) that are synchronized with the clock speed that the microprocessor is optimized for. This tends to increase the number of instructions that the processor can perform in a given time. The speed of SDRAM is rated in MHz rather than in nanoseconds (ns). This makes it easier to compare the bus speed and the RAM chip speed. You can convert the RAM clock speed to nanoseconds by dividing the chip speed into 1 billion ns (which is one second). For example, an 83 MHz RAM would be equivalent to 12 ns.
With older clocked electronic circuits, the transfer rate was one per full cycle of the clock signal. This cycle is called rise and fall. A clock signal changes two times per transfer, but the data lines change no more than one time per transfer. This restriction can cause integrity (data corruption and errors during transmission) when high bandwidths are used. SDRAM transmits signals once per clock cycle. The newer DDR transmits twice per clock cycle.
SDRAM is improved DRAM with a synchronous interface waiting for a clock pulse before it responds to data input. SDRAM uses a feature called pipelining, which accepts new data before finishing processing previous data. A delay in data processing is called latency.
DRAM technology has been used since the 1970’s. In 1993, SDRAM was implemented by Samsung with model KM48SL2000 synchronous DRAM. By 2000, DRAM was replaced by SDRAM. In the beginning SDRAM was slower than burst EDO DRAM because of the extra logic features. But the benefits of SDRAM allowed more than one set of memory, which increased the bandwidth efficiency.
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